| DESIGN FUNCTION AND QUANTITY | 3 GATE, NAND |
| FEATURES PROVIDED | MONOLITHIC AND HERMETICALLY SEALED AND POSITIVE OUTPUTS AND MEDIUM SPEED |
| INCLOSURE CONFIGURATION | DUAL-IN-LINE |
| INCLOSURE MATERIAL | CERAMIC AND GLASS |
| BODY HEIGHT | 0.055 INCHES MINIMUM AND 0.140 INCHES MAXIMUM |
| BODY LENGTH | 0.745 INCHES MINIMUM AND 0.770 INCHES MAXIMUM |
| BODY WIDTH | 0.240 INCHES MINIMUM AND 0.260 INCHES MAXIMUM |
| CASE OUTLINE SOURCE AND DESIGNATOR | -0-001-AD JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| INPUT CIRCUIT PATTERN | TRIPLE 3 INPUT |
| OUTPUT LOGIC FORM | COMPLEMENTARY-METAL OXIDE-SEMICONDUCTOR LOGIC |
| MAXIMUM POWER DISSIPATION RATING | 200.0 MILLIWATTS |
| OPERATING TEMP RANGE | -55.0 TO 125.0 CELSIUS |
| STORAGE TEMP RANGE | -65.0 TO 150.0 CELSIUS |
| TERMINAL SURFACE TREATMENT | SOLDER |
| TERMINAL TYPE AND QUANTITY | 14 PRINTED CIRCUIT |
| TIME RATING PER CHACTERISTIC | 100.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 100.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |
| VOLTAGE RATING AND TYPE PER CHARACTERISTIC | 15.5 VOLTS MAXIMUM POWER SOURCE |